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The 1st IEEE International Workshop on Reengineering for Parallelism in Heterogeneous Parallel Platforms
held in conjunction with IEEE ISPA-15

August 20-22, 2015, Helsinki, Finland

In recent years, traditional processors have not been able to directly translate chip fabrication-technology advances intro performance gains. To keep satisfying the demand for computing power, there is a shift from homogeneous machines to heterogeneous architectures combining different kinds of processors (CPUs, GPUs, DSPs, FPGAs, and other accelerators). While this approach has allowed significant performance and energy efficiency benefits, heterogeneous systems are often highly difficult to program with existing tools. To reduce the cost of system development, reengineering techniques emerge as a solution which may help to balance ease-of-development with better performance, better reliability, and lower maintenance costs.

The RePara2015 workshop is organized in cooperation with European Projects REPARA, POLCA, and RePhrase, and it aims to join experts from related disciplines to share recent advances in different areas contributing to better transformation of new and legacy applications to different programming models for diverse computing devices in the context of parallel heterogeneous architectures.

Scope and Interests

Topics of interest include, but are not limited to:

  • High-level parallel programming models, libraries and languages for heterogeneous platforms
  • Description languages for Heterogeneous Parallel Platforms
  • Parallel patterns for Heterogeneous Platforms
  • Autonomic management of Power/Performance tradeoffs
  • Automated kernel identification and assessment
  • Software refactoring approaches for parallel programming models
  • Transformations from source code to reconfigurable hardware
  • Integration of FPGA accelerators into refactored software
  • Runtimes for software coordination in heterogeneous parallel platforms
  • Performance modeling and prediction in heterogeneous parallel platforms
  • Energy efficiency monitoring and prediction in heterogeneous parallel platforms
  • Software quality assessment in parallel programming models with special attention to maintainability
  • Applying partitioning and mapping for parallel heterogeneous computing architectures
  • Application experiences of refactoring to software in industrial domains

Submission Instructions

Papers submitted to the workshop should be written in English conforming to the IEEE Conference Proceedings Format (8.5" x 11", Two-Column). The paper should be submitted through the workshop submission system at the workshop website. The length of the papers should not exceed 6 pages + 2 pages for over length charges.

Accepted and presented papers will be included into the IEEE Conference Proceedings published by IEEE CS CPS and submitted to IEEE Xplore and CSDL. Authors of accepted papers, or at least one of them, are requested to register and present their work at the conference, otherwise their papers will be removed from the digital libraries of IEEE CS after the conference. Distinguished papers presented at the conference, after further revision, will be recommended to special issues of reputable SCI/EI-indexed journals.

Submitting a paper to the workshop means that, if the paper is accepted, at least one author should attend the workshop and present the paper.

Journal Publication

Extended version of selected papers from the workshop will be invited by the RePara2015 program committee for publication, after further revision, in an special issue of Journal of Supercomputing (Springer, ISSN: 0920-8542, Impact Factor 2013: 0.841).

Important Dates

Submission deadline: May 10th, 2015 (this is a firm deadline)
Authors notification: May 31st, 2015
Camera-ready due: July 1st, 2015
Registration: July 1st, 2015

Program Co-Chairs

J. Daniel Garcia, University Carlos III of Madrid, Spain
Prof. Kevin Hammond, University of St. Andrews University
Prof. Lutz Schubert, University of Ulm, Germany

PC Members (in alphabetical order)

Prof. Marco Aldinucci, University of Torino, Italy
Dr. Christopher Brown, University of St. Andrews, United Kingdom
Prof. Marco Danelutto, University of Pisa, Italy
Dr. Rudolf Ferenc, University of Szeged, Hungary
Dr. Javier Garcia-Blas, University Carlos III of Madrid, Spain
Prof. Sergei Gortlatch, University of Muenster, Germany
Dr. Jose Gracia, HLRS, University of Stuttgart, Germany
Dr. Akos Kiss, University of Szeged, Hungary
Prof. Jan Kuper, University of Twente, Netherlands
Prof. Andreas Koch, Technische Universität Darmstadt, Germany
Dr. Luis M. Sanchez, University Carlos III of Madrid Spain
Prof. Peter Sommerlad, HSR, Switzerland
Dr. Christian Simmendinger, T-Systems, Germany
Dr. Zsolt Szepessy, Evopro Innovations, Hungary
Dr. Massimo Torquati, University of Pisa, Italy
Dr. Jorge Villagra, Ixion Industry and Aerospace, Spain
Dr. John Wickerson, Imperial College, United Kingdom


Please email inquiries concerning the workshop to J. Daniel Garcia.

Aalto ELEC